EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 52

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
2–46
Preliminary
to automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
registers.
There are two paths in the IOE for a combinatorial input to reach the logic
array. Each of the two paths can have a different delay. This allows you
adjust delays from the pin to internal LE registers that reside in two
different areas of the device. The designer sets the two combinatorial
input delays by selecting different delays for two different paths under
the Decrease input delay to internal cells logic option in the Quartus II
software. When the input signal requires two different delays for the
combinatorial input, the input register in the IOE is no longer available.
The IOE registers in Cyclone devices share the same source for clear or
preset. The designer can program preset or clear for each individual IOE.
The designer can also program the registers to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device's active-low input
upon power up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that same signal if they require preset or
clear. Additionally a synchronous reset signal is available to the designer
for the IOE registers.
External RAM Interfacing
Cyclone devices support DDR SDRAM and FCRAM interfaces at up to
133 MHz through dedicated circuitry.
DDR SDRAM & FCRAM
Cyclone devices have dedicated circuitry for interfacing with DDR
SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins.
However, the configuration input pins in bank 1 must operate at 2.5 V
because the SSTL-2 V
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Table 2–9. Cyclone Programmable Delay Chain
Programmable Delays
Table 2–9
shows the programmable delays for Cyclone devices.
CCIO
level is 2.5 V. Additionally, the configuration
Decrease input delay to internal cells
Decrease input delay to input registers
Increase delay to output pin
Quartus II Logic Option
Altera Corporation
January 2007