EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 11

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–4. LAB-Wide Control Signals
Logic Elements
Altera Corporation
January 2007
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
6
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack
allows clock and control signal distribution in addition to data.
shows the LAB control signal generation circuit.
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See
labclk1
labclkena1
labclk2
Figure
labclkena2
2–5.
asyncload
or labpre
TM
syncload
interconnect's inherent low skew
labclr1
labclr2
Logic Elements
synclr
Preliminary
Figure 2–4
addnsub
2–5