EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 97

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
January 2007
Note to
(1)
Decrease input delay to
internal cells
Decrease input delay to input
register
Increase delay to output pin
Table 4–47. Cyclone IOE Programmable Delays on Row Pins
EPC1C3 devices do not support the PCI I/O standard
Table
Parameter
4–47:
Maximum Input & Output Clock Rates
Tables 4–48
row pins in Cyclone devices.
Off
Small
Medium
Large
On
Off
On
Off
On
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins
Setting
I/O Standard
and
-6 Speed Grade
Min
4–49
show the maximum input clock rate for column and
2,212
2,639
3,057
3,057
Max
154
154
556
0
0
-6 Speed
Grade
464
392
387
387
405
405
414
464
473
567
-7 Speed Grade
Min
2,543
3,034
3,515
3,515
-7 Speed
Max
177
177
639
Grade
0
0
356
365
428
432
428
302
311
320
374
549
-8 Speed Grade
Min
-8 Speed
Grade
387
207
252
243
333
293
302
396
396
531
2,875
3,430
3,974
3,974
Max
200
200
722
Timing Model
0
0
Preliminary
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
4–27
ps
ps
ps
ps
ps
ps
ps
ps
ps