EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 80

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
4–10
Preliminary
Clock tree
f
LE
M A X
Parameter
Table 4–19. Clock Tree Maximum Performance Specification
Table 4–20. Cyclone Device Performance
Resource
Used
16-to-1
multiplexer
32-to-1
multiplexer
16-bit counter
64-bit counter
Maximum frequency
that the clock tree
can support for
clocking registered
logic
Design Size &
Function
Definition
(1)
Performance
The maximum internal logic array clock tree frequency is limited to the
specifications shown in
Table 4–20
designs. All performance values were obtained with the Quartus II
software compilation of library of parameterized modules (LPM)
functions or megafunctions. These performance values are based on
EP1C6 devices in 144-pin TQFP packages.
-
-
-
-
Mode
Min
-6 Speed Grade
shows the Cyclone device performance for some common
Typ
LEs
21
44
16
66
Max
405
Resources Used
Memory
Table
M4K
Bits
Min
-
-
-
-
-7 Speed Grade
4–19.
Memory
Typ
Blocks
M4K
-
-
-
-
Max
320
-6 Speed
405.00
317.36
405.00
208.99
Grade
(MHz)
Min
-8 Speed Grade
Performance
-7 Speed
Typ
320.00
284.98
320.00
181.98
Altera Corporation
Grade
(MHz)
January 2007
Max
275
-8 Speed
275.00
260.15
275.00
160.75
Grade
(MHz)
Units
MHz