EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 4

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
Features
1–2
Preliminary
Note to
(1)
LEs
M4K RAM blocks (128 × 36 bits)
Total RAM bits
PLLs
Maximum user I/O pins
Table 1–1. Cyclone Device Features
This parameter includes global clock pins.
Table
Feature
1–1:
(1)
The Cyclone device family offers the following features:
■
■
■
■
■
■
■
■
■
■
■
■
2,910 to 20,060 LEs, see
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66- and 33-MHz, 64- and 32-bit PCI standard
High-speed (640 Mbps) LVDS I/O support
Low-speed (311 Mbps) LVDS I/O support
311-Mbps RSDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera
Program (AMPP
59,904
EP1C3
2,910
104
13
®
1
MegaCore
SM
78,336
EP1C4
4,000
®
) megafunctions.
301
17
functions and Altera Megafunctions Partners
2
Table 1–1
92,160
EP1C6
5,980
185
20
2
239,616
EP1C12
12,060
249
52
2
Altera Corporation
January 2007
294,912
EP1C20
20,060
301
64
2