EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 83

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 4–1. Dual-Port RAM Timing Microparameter Waveform
Altera Corporation
January 2007
unreg_data-out
reg_data-out
wraddress
rdaddress
data-in
rdclock
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
an
din
Figure 4–1
shown in
t
t
t
R4
C4
LOCAL
Table 4–24. Routing Delay Internal Timing Microparameter Descriptions
t
doutn-1
WEREH
doutn
Symbol
a0
b0
Table
shows the memory waveforms for the M4K timing parameters
t
t
DATACO1
WEREH
4–23.
t
DATACO2
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Local interconnect delay
a1
t
RC
doutn
dout0
a2
b1
t
t
WADDRSU
a3
WERESU
Parameter
dout0
din4
a4
b2
t
WADDRH
din5
a5
Timing Model
Preliminary
b3
din6
a6
4–13