EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 99

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
January 2007
f
f
t
f
clock output)
IN
IN
IN
OUT_EXT
Table 4–52. Cyclone PLL Specifications (Part 1 of 2)
DUTY
JITTER
(external PLL
Symbol
Input frequency (-6 speed
grade)
Input frequency (-7 speed
grade)
Input frequency (-8 speed
grade)
Input clock duty cycle
Input clock period jitter
PLL output frequency
(-6 speed grade)
PLL output frequency
(-7 speed grade)
PLL output frequency
(-8 speed grade)
PLL Timing
Table 4–52
Note to
(1)
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
3.3-V PCI
LVDS
Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins
EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
I/O Standard
Parameter
Tables 4–50
(1)
describes the Cyclone FPGA PLL specifications.
through 4–51:
-6 Speed
Grade
296
381
286
219
367
169
160
160
131
320
66
15.625
15.625
15.625
15.625
15.625
15.625
40.00
Min
-7 Speed
Grade
166
151
151
123
285
366
277
208
356
303
66
±
Max
-8 Speed
464
428
387
320
320
275
60
200
Grade
273
349
267
195
343
162
146
142
115
275
66
Timing Model
Preliminary
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
%
4–29