MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 114

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

System Integration Block (SIB)
LPP16—Low-power Clock Prescale Divide by 16
LPREC—Low-Power Recovery
3.9 CLOCK CONTROL REGISTER
The CKCR is a 16-bit register is a memory-mapped read-write register. The address of this
register is fixed at $0FA in supervisor data space (FC = 5). This register controls the state
of CLKO, RCLK1, TCLK1, and BRG1. This register is cleared at reset.
CLKOM—CLKO Mode
TSTCLK1—Three-state TCLK1
3-64
After a system reset, this bit defaults to zero.
After a system reset, the bit defaults to zero.
These bits may be written at any time to change the mode of the CLKO pin. Changes to
CLKO are made while the CLKO signal is high. No spikes on CLKO will occur when the
CLKOM bits are changed.
0 = The low-power clock divider input clock is the main clock.
1 = The low-power clock divider input clock is the main clock divided by 16. Thus,
0 = Nondestructive recovery from low power. The processor returns to full frequency
1 = Destructive recovery from low power. The processor returns to full frequency and
00 = The CLKO pin functions normally
01 = The CLKO pin output driver is two thirds its normal strength. Specification 5a at
01 = The CLKO pin output driver is one third its normal strength. Specification 5a at
11 = The CLKO pin output is disabled, but is driven high by an internal pullup. Signifi-
0 = Normal operation
1 = The TCLK1 pin is three-stated. This option may be used to prevent contention on
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CLKOM
a divide ratio of 32 to 1024 (LPCD4—LPCD0 0 to 31) can be selected.
and then proceeds using currently held status value. This is called low-power
mode.
then drives RESET for 16 clock cycles. This is called lowest power mode.
the TCLK1 pin if an external clock is provided to the TCLK1 pin while the SCC1
baud rate generator is output on TCLK1. This option may also be chosen if it is re-
quired to run the SCC1 baud rate generator at high speed (for instance in a high
speed UART application), but the TCLK1 output is not needed, and it is desired to
16.67 MHz is 2 to 14 ns and at 20 MHz is 2 to 11 ns. The output drive derating
factor for CLKO in this mode is not specified.
16.67 MHz is 2 to 20ns and at 20 MHz is 2 to 16ns. The output drive derating fac-
tor for CLKO in this mode is not specified.
cant power savings can be obtained by disabling CLKO. Typical power savings
may range between 2 and 6 mA, depending on the CLKO loading. Disabling
CLKO can also reduce noise and electromagnetic interference on the printed cir-
cuit board.
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TSTCLK1 TSRCLK1 DBRG1
13
12
11
MC68302 USER’S MANUAL
10
9
8
7
6
RESERVED
5
4
3
2
1
MOTOROLA
0