MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 431

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

RXB—Rx Buffer
E.1.1.2.5 HDLC Mask Register (SCCM). This 8-bit register is located at offset $88A
(SCC1), $89A (SCC2), and $8AA (SCC3) on D15-D8 of a 16-bit data bus. The SCCM is
used to enable and disable interrupt events reported by the SCCE. The mask bits corre-
spond to the interrupt event bit shown in the SCCE. A bit should be set to one to enable the
corresponding interrupt in the SCCE.
E.1.1.2.6 HDLC Status Register (SCCS). This 8-bit register is located at offset $88C
(SCC1), $89C (SCC2), and $8AC (SCC3) on D15-D8 of a 16-bit data bus. The SCCS reg-
ister reflects the current status of the RXD, CD, and CTS lines as seen by the SCC.
ID—Idle Status on the Receiver Line (valid only when the ENR bit is set and the receive
clock is running)
CD—Carrier Detect Status Changed (valid only when the ENR bit is set and the receive
clock is running)
CTS—Clear-To-Send Status Changed (valid only when the ENT bit is set and the transmit
clock is running)
E.1.1.3 GENERAL AND HDLC PROTOCOL-SPECIFIC PARAMETER RAM. Each
has 32 words of parameter RAM used to configure receive and transmit operation, store
temporary parameters for the CP, and maintain counters. The first 14 words are general
parameters, which are the same for each protocol. The last 18 words are specific to the pro-
tocol selected. The following sections discuss the parameters that the user must initialize to
configure the HDLC operation.
E.1.1.3.1 RFCR/TFCR—Rx Function Code/Tx Function Code. This 16-bit parameter
contains the function codes of the receive data buffers and transmit data buffers. The user
must initialize the function codes (FC2-FC0) to a value less than 7.
MOTOROLA
0 = No interrupt
1 = A buffer that was not a complete frame was received on the HDLC channel (set
0 = Receiver line is not idling.
1 = Either CD is not asserted or the receiver line is idling while CD is asserted.
0 = CD is asserted.
1 = CD is not asserted.
0 = CTS is asserted.
1 = CTS is not asserted.
only if the I bit in the Rx buffer descriptor is set).
CTS
—
7
7
CD
—
6
6
MC68360 USER’S MANUAL
IDL
—
5
5
TXE
—
4
4
RXF
—
3
3
BSY
ID
2
2
TXB
CD
1
1
RXB
CTS
SCC Programming Reference
0
0
SCC
E-9