MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 55

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

REQG—Request Generation
SAPI—Source Address Pointer (SAP) Increment
DAPI—Destination Address Pointer (DAP) Increment
SSIZE—Source Size
DSIZE—Destination Size
BT—Burst Transfer
MOTOROLA
The following decode shows the definitions for the REQG bits:
The following decode shows the definitions for the SSIZE bits.
The following decode shows the definitions for the DSIZE bits.
The BT bits control the maximum percentage of the M68000 bus that the IDMA can use
during each 1024 clock cycle period following the enabling of the IDMA. The IDMA runs
for a consecutive number of cycles up to its burst transfer percentage if bus clear (BCLR)
is not asserted and the BCR is greater than zero. The following decode shows these per-
centages.
00 = Internal request at limited rate (limited burst bandwidth) set by burst transfer (BT)
01 = Internal request at maximum rate (one burst)
10 = External request burst transfer mode (DREQ level sensitive)
11 = External request cycle steal (DREQ edge sensitive)
0 = SAP is not incremented after each transfer.
1 = SAP is incremented by one or two after each transfer, according to the source size
0 = DAP is not incremented after each transfer.
1 = DAP is incremented by one or two after each transfer, according to the destination
00 = Reserved
01 = Byte
10 = Word
11 = Reserved
00 = Reserved
01 = Byte
10 = Word
11 = Reserved
00 = IDMA gets up to 75% of the bus bandwidth.
01 = IDMA gets up to 50% of the bus bandwidth.
10 = IDMA gets up to 25% of the bus bandwidth.
11 = IDMA gets up to 12.5% of the bus bandwidth.
(SSIZE) bits and the starting address.
size (DSIZE) bits and the starting address.
bits
An interrupt will only be generated if the IDMA bit is set in the
IMR.
MC68302 USER’S MANUAL
NOTE
System Integration Block (SIB)
3-5