MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 204

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Communications Processor (CP)
rate generator or from external pins. More information on the baud rate generator is avail-
able in 4.5.2 SCC Configuration Register (SCON).
4.5.13.1 Bisync Channel frame Transmission Processing
The BISYNC transmitter is designed to work with almost no intervention from the M68000
core. When the M68000 core enables the BISYNC transmitter, it will start transmitting
SYN1–SYN2 pairs (located in the data synchronization register) or idle as programmed in
the BISYNC mode register. The BISYNC controller polls the first buffer descriptor (BD) in
the transmit channel's BD table. When there is a message to transmit, the BISYNC control-
ler will fetch the data from memory and start transmitting the message (after first transmitting
the SYN1–SYN2 pair).
When a BD's data has been completely transmitted, the last in message (L) bit is checked.
If both the L bit and transmit BCS bit are set in that BD, the BISYNC controller will append
the CRC16/LRC. Subsequently, the BISYNC controller writes the message status bits into
the BD and clears the ready bit. It will then start transmitting SYN1–SYN2 pairs or IDLEs as
programmed in the BISYNC mode register. When the end of the current BD has been
reached and the last bit is not set (working in multibuffer mode), only the ready bit is cleared.
In both cases, an interrupt is issued according to the interrupt (I) bit in the BD. By appropri-
ately setting the I bit in each BD, interrupts can be generated after the transmission of each
buffer, a specific buffer, or each block. The BISYNC controller will then proceed to the next
BD in the table.
If no additional buffers have been presented to the BISYNC controller for transmission, an
in-frame underrun is detected, and the BISYNC controller begins transmitting SYNCs. If the
BISYNC controller was in transparent mode, the BISYNCs controller transmits DLE-SYNC
pairs. This case is not an error. However, if an underrun occurs within a buffer, the BISYNC
controller will transmit a SYN1–SYN2 pair followed by either SYNCs or idles according to
the SYNF bit in the BISYNC mode register. This case is an underrun error and is described
further in 4.5.13.8 BISYNC Error-Handling Procedure.
4-84
• Flexible Data Buffers
• Eight Control Character Recognition Registers
• Automatic SYNC1 and SYNC2 Detection
• SYNC/DLE Stripping and Insertion
• CRC16 and LRC Generation/Checking
• Parity (VRC) Generation/Checking
• Supports BISYNC Transparent Operation (Use of DLE Characters)
• Supports Promiscuous (Totally Transparent) Reception and Transmission
• Maintains Parity Error Counter
• External SYNC Support
• Reverse Data Mode
• Four Commands
MC68302 USER’S MANUAL
MOTOROLA