MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 354

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68302 Applications
circuit will also place the MC68302 into reset if V
drops below a threshold, an advantage
cc
over a simple RC circuit.
D.1.3 Memory Interface
AS, R/W, UDS, LDS, A23–A1, D15–D0, CS0, and CS1 are used in the memory interface.
The bidirectional control signals have pullups so that they are inactive when the MC68302
is not actively driving them. CS0 and CS1 are only outputs and do not need pullups.
DTACK is generated internally by the wait-state generation logic, and therefore it does not
need to be externally connected. It is driven by the wait-state generation logic during chip-
select accesses and is pulled up externally through a resistor.
BCLR is an open-drain signal that is output by the MC68302 when the SDMA requests the
bus or (if enabled) when an interrupt request is pending. It is therefore pulled up externally.
D.1.4 Memory Circuit
The EPROM design is a straight connection. Larger EPROM sizes may be easily substitut-
ed; it is also possible to use a single 16-bit EPROM, if desired, and reduce the component
count by one.
CS0 is used to select the EPROM since CS0 is designed to be used for a boot ROM. CS0
comes up enabled for the first 8 kbytes of the system address space. Before the program
jumps outside of this space, it should configure the CS0 range for 32 kbytes and enable the
RAM chip select to cover the RAM range and desired starting address. To switch the RAM
down to low-order memory to allow exception vectors to be altered, see D.2 Switching the
External ROM and RAM Using the MC68302 .
LDS and UDS define the lower and upper bytes of the program word, respectively, and are
connected to the EPROM output enable.
The RAM design is similar to the EPROM design, except that the R/W signal is used to qual-
ify the output enable and the LDS/UDS signals are used to qualify whether to write the par-
ticular byte of the data word (the M68000 supports byte operations).
CS1 is used to select the RAM.
No external buffers are required in this small system design.
D.1.5 Memory Timing Analysis
The design as shown will work with zero wait states with a 100-ns EPROM and a static RAM,
such as the MCM6202. The RAM writes are controlled by the enable (E) rather than by the
write (W). Two of the MC68302 required specifications deserve special note.
The time between CS low and data valid must be calculated for proper timing of read cycles.
This time is approximately 2 1/2 clocks. CS is asserted by the MC68302 after the rising edge
of S2. Data must be valid a setup time before the S6 falling edge. Thus, for a 16.67-MHz
device, the equation for the time between CS low and data valid is as follows:
D-4
MC68302 USER’S MANUAL
MOTOROLA