MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 394

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68302 Applications
method works because the parallel I/O lines default as inputs to the MC68302 and can
therefore all be pulled high initially. After the slave BARs are programmed, the parallel l/O
lines on the master should be reconfigured as inputs; otherwise, a contention could occur
on A23 when a slave's DMA is accessing the bus.
This method is the easiest because it requires no external glue. It costs one parallel l/O line
per slave on the master MC68302 and reduces the address space of each slave from 16
MB to 8 MB, neither of which should be a problem in most systems. If A23 is really needed
on the slaves, it can be regained, but extra logic is required.
D.7.4 Dealing with Interrupts
The following example is the easiest method for dealing with interrupts from the slaves. It
assumes that any other external interrupt sources are sent directly to the master MC68302
without using the interrupt controllers on the slaves.
Why not use the vector generation enable (VGE) bit in each slave MC68302 to allow the
slaves to generate different vectors for each of their internal peripherals? This could be
done; however, the slaves must be tricked into responding to an unique interrupt level (or
else multiple vectors could collide on the bus simultaneously). The external decoding and
address buffer logic required to do this slows down the interface timing (and adds expense).
Rather, the VGE bit is intended for applications where a single MC68302 is a slave to an-
other processor such as the MC68020.
To use the interrupt controller on a slave MC68302 (in either normal or dedicated mode) to
handle interrupt levels 1, 6, or 7 from an external peripheral, connect the slave's lOUT2-
lOUT0 pins directly to the master's lPL2-lPL0 pins. The master MC68302 will supply the vec-
tor for levels 1, 6, and 7, and level 4 of the slave will be interpreted as an error vector
(00000). Upon branching to this vector, the master MC68302 software should then check
the slave's IPR to identify the source.
D.7.5 Arbitration
If only one slave is present, no arbiter is required because the BR as an output on the slave
can be sent directly to the BR input on the master. Figure D-20 shows a dual master-slave
system using this arbitration scheme. Note that the BCLR pin from the slave MC68302 can
be used to give the 12 SDMA channels in the system priority over the two IDMA channels
in the system. BCLR is asserted whenever an SDMA channel wants the bus, and, will tem-
D-44
1. The internal interrupts cause the slaves to force out level 4 on their lOUT2-lOUT0 pins.
2. IOUT2 from the slave is connected to the master PB8, PB9, PB10, or PB11 pin if the
3. The best method of operation is for the slaves not to generate the vector during the
(AVEC, RMC, and CS0 are not available on the slaves.)
master is in normal interrupt mode, or to IRQ1 or IRO6 if it is in dedicated interrupt
mode. Thus, in normal mode the slave interrupts will arrive at level 4, and in dedicated
mode they will arrive at either level 1 or 6.
interrupt acknowledge cycle. The master MC68302 can generate it and then read the
IPR of the slave to determine the actual source of the interrupt.
MC68302 USER’S MANUAL
NOTE
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