MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 286

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Signal Description
5.19 PARALLEL I/O PINS WITH INTERRUPT CAPABILITY
The four parallel I/O pins with interrupt are shown in Figure 5-16.
PB11–PB8—Port B Parallel I/O pins
These four pins may be configured as a general-purpose parallel I/O ports with interrupt ca-
pability. Each of the pins can be configured either as an input or an output. When configured
as an input, each pin can generate a separate, maskable interrupt on a high-to-low transi-
tion. PB8 may also be used to request a refresh cycle from the DRAM refresh controller rath-
er than as an I/O pin. The input buffers have Schmitt triggers.
5.20 CHIP-SELECT PINS
The chip-select pins are shown in Figure 5-17.
CS0/IOUT2—Chip-Select 0/Interrupt Output 2
In normal operation, this pin functions as CS0. CS0 is one of the four active-low output pins
that function as chip selects for external devices or memory. It does not activate on access-
es to the internal RAM or registers (including the BAR, SCR, or CKCR registers).
When the M68000 core is disabled, this pin operates as IOUT2. IOUT2—IOUT0 provide the
interrupt request output signals from the IMP interrupt controller to an external CPU when
the M68000 core is disabled.
5-22
Figure 5-16. Port B Parallel I/O Pins with Interrupt
Figure 5-17. Chip-Select Pins
MC68302 USER’S MANUAL
MC68302
MC68302
CS0 / IOUT2
CS3–CS1
PB8
PB9
PB10
PB11
MOTOROLA