MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 160

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Communications Processor (CP)
Bits 7–3—Reserved for future use.
ID—Idle Status on the Receiver Line
CD—Carrier Detect Status on the Channel Pin
CTS —Clear-to-Send Status on the Channel Pin.
When the CTS and CD lines are programmed to software control in the SCC mode register,
these lines do not affect the SCC and can be used for other purposes such as a data set
ready (DSR), a data terminal ready (DTR) line, or an interrupt source in the SCCE register
according to the behavior just described.
4.5.8.4 Bus Error on SDMA Access
4-40
This bit is meaningful only if the SCC is programmed to HDLC or UART mode. In HDLC
mode, this bit is a one after 15 continuous ones are received on the line. This bit will be
zero after a single zero occurs on the line. If flags, rather than idles, are received between
frames, the ID bit will remain zero between frames.
In UART mode, this bit is a one after one idle character (9 to 13 bits) is received and is a
zero after a single zero occurs on the line (e.g., a start bit).
If the DIAG1–DIAG0 bits in the SCM are programmed to normal mode, then the CD signal
is an enable signal for ID status. In this case, if CD is not asserted, the ID bit will always
be one, regardless of the activity on the line.
If the DIAG1–DIAG0 bits in the SCM are programmed to software operation mode, then
the ID bit will always reflect line activity, regardless of the state of the CD pin.
The ID bit is valid in both the multiplexed and nonmultiplexed modes, once the ENR bit is
set.
This bit has the same polarity as the external pin. In the multiplexed modes, it is always
zero. CD is undefined until ENR is set.
This bit has the same polarity as the external pin. In the PCM highway mode, it is always
zero. In the GCI and IDL mode, if the SCC is connected to the D channel, then this bit is
valid; otherwise, it is always zero. CTS is undefined until the ENT bit is set.
When a bus error occurs on an access by the SDMA channel, the CP generates a unique
interrupt (see 3.2 Interrupt Controller). The interrupt service routine should read the bus
error channel number from the parameter RAM at BASE + 67C as follows:
0—SCC1 Tx Channel
1—SCC1 Rx Channel or DRAM Refresh Cycle
2—SCC2 Tx Channel
3—SCC2 Rx Channel
gardless of what happens externally. This signifies that the cor-
responding SCCS bit is now valid.
7
RESERVED
MC68302 USER’S MANUAL
3
ID
2
CD
1
CTS
0
MOTOROLA