LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet
LAN9211_0711
Related parts for LAN9211_0711
LAN9211_0711 Summary of contents
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PRODUCT FEATURES Highlights Optimized for medium to high performance applications Efficient architecture with low CPU overhead Easily interfaces to most 16-bit embedded CPU’s Integrated PHY with HP Auto-MDIX Integrated checksum offload engine helps reduce CPU load Low pin count and ...
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LAN9211-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 0.1 Customer Datasheet Revision History Table 0.1 Customer Datasheet Revision History Table REVISION SECTION/FIGURE/ENTRY Rev. 1.93 Standard SMSC formatting applied throughout document. (11-26-07) Rev. 1.92 Chapter 2 Pin Description ...
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Table of Contents 0.1 Customer Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 3.12.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INT_EN—Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 6.3 PIO Burst Reads ...
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List of Figures Figure 1.1 System Block Diagram ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet List of Tables Table 0.1 Customer Datasheet Revision History Table ...
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Chapter 1 General Description The LAN9211 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9211 has been specifically designed to provide the highest performance ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet System Memory Microprocessor/ System Bus Microcontroller The SMSC LAN9211 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller ...
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Internal Block Overview This section provides an overview of each of these functional blocks as shown in Block Diagram". PME Wakup Indicator Power Management Host Bus Interface (HBI) 16-bit SRAM I/F PIO Controller Interrupt IRQ Controller FIFO_SEL GP Timer ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The ...
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Host Bus Interface (SRAM Interface) The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the LAN9211 Control and Status Registers (CSR’s). The host bus interface is the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Chapter 2 Pin Description and Configuration IRQ 43 TPO- 44 TPO+ 45 VDD_A33 46 TPI- 47 TPI+ 48 VDD_A33 49 EXRES1 50 VDD_A33 51 AMDIX_EN 52 VDD_A18 53 XTAL2 ...
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Pin List NAME SYMBOL Host Data D[15:0] Host Address A[7:1] Read Strobe nRD Write Strobe nWR Chip Select nCS Interrupt IRQ Request FIFO Select FIFO_SEL NAME SYMBOL TPO+ TPO+ TPO- TPO- TPI+ TPI+ TPI- TPI- PHY External Bias EXRES1 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Table 2.3 Serial EEPROM Interface Signals NAME SYMBOL EEPROM Data, EEDIO/GPO3/ GPO3, TX_EN, TX_EN/TX_CLK TX_CLK EEPROM Chip EECS Select EEPROM Clock, EECLK/GPO4/ GPO4 RX_DV, RX_DV/RX_CLK RX_CLK LAN9211 SMSC BUFFER ...
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NAME SYMBOL Crystal 1, Clock In XTAL1/CLKIN Crystal 2 XTAL2 Reset nRESET Wakeup Indicator PME Auto-MDIX Enable AMDIX_EN No Connect NC Revision 1.93 (11-27-07) High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Table 2.4 System and Power Signals ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Table 2.4 System and Power Signals (continued) NAME SYMBOL General Purpose GPIO[2:0]/ I/O data, nLED[3:1] nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), nLED3 (Full- Duplex Indicator ). +3.3V ...
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Table 2.5 56-QFN Package Pin Assignments PIN PIN NUM PIN NAME NUM 1 VDD_IO 15 2 VDD_CORE 16 3 GPIO0/nLED1 17 4 GPIO1/nLED2 18 5 GPIO2/nLED3 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 2.2 Buffer Types TYPE Input pin I Schmitt triggered Input IS Output with 12mA sink and 12mA source O12 Open-drain output with 12mA sink OD12 I/O with 8mA symmetrical ...
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Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet The LAN9211 can store up to 250 Ethernet packets utilizing FIFOs, totaling 16K bytes, with a packet granularity of 4 bytes. This memory is shared by the RX and ...
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Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The first bit of the destination address signifies whether it is ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Table 3.1 Address Filtering Modes (continued) MCPAS PRMS INVFILT 3.4 Filtering Modes 3.4.1 Perfect Filtering This filtering mode passes ...
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Wake-up Frame Detection Setting the Wake-Up Frame Enable bit (WUEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9211 MAC in the wake-up frame detection mode. In this mode, normal data reception is disabled, and detection logic within ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Table 3.3 Filter i Byte Mask Bit Definitions FIELD DESCRIPTION 31 Must be zero (0) 30:0 Byte Mask: If bit j of the byte mask is set, the CRC ...
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Magic Packet Detection Setting the Magic Packet Enable bit (MPEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9211 MAC in the “Magic Packet” detection mode. In this mode, normal data reception is disabled, and detection logic within ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 3.6.1 Receive Checksum Offload Engine (RXCOE) The receive checksum offload engine provides assistance to the CPU by calculating a 16-bit checksum for a received Ethernet frame. The RXCOE readily ...
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DST SRC 1DWORD Figure 3.5 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16 DST SRC ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet {DSAP, SSAP, CTRL, OUI[23:16 DST SRC ...
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Transmit Checksum Offload Engine (TXCOE) The transmit checksum offload engine provides assistance to the CPU by calculating a 16-bit checksum, typically for TCP, for a transmit Ethernet frame. The TXCOE calculates the checksum and inserts the results back into ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Note: The TX checksum preamble must be DWORD-aligned (i.e., the two least significant bits of the Data Start Offset fields in TX Command “A” must be zero). Any valid ...
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Note: CSR and status FIFO accesses are not affected by the FPORTEND and FSELEND endianess select bits. 3.7.4 Word Swap Function In addition to mixed endian functionality, the LAN9211 supports a Word Swap Function. This feature is controlled by the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BIG ENDIAN (FPORTEND = 1 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 1 for Data FIFO direct access when FIFO_SEL=1) INTERNAL FIFO ORDER MSB 31 ...
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Table 3.8 Endian Ordering Logic Operation A1=1 FPORTEND=0 FSELEND=0 A1=0 A1=1 FPORTEND=1 FSELEND=0 A1=0 A1=1 FPORTEND=0 FSELEND=1 A1=0 A1=1 FPORTEND=1 FSELEND=1 A1=0 A1=1 FPORTEND=0 FSELEND=0 A1=0 A1=1 FPORTEND=1 FSELEND=0 A1=0 A1=1 PORTEND=0 FSELEND=1 A1=0 A1=1 PORTEND=1 FSELEND=1 A1=0 3.8 General ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 3.9 EEPROM Interface The LAN9211 can optionally load its MAC address from an external serial EEPROM properly configured EEPROM is detected by the LAN9211 at power-up, hard ...
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If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9211 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. Figure 3.4, "EEPROM Access Flow Diagram" EEPROM Read or ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The ...
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EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) EWEN (Erase/Write Enable): Enables the EEPROM for erase and write operations. The EEPROM ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA ...
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WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 3.10 Power Management The LAN9211 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various ...
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Note 3.13 The host must only perform read accesses prior to the ready bit being set. Once the READY bit is set, the LAN9211 is ready to resume normal operation. At this time the WUPS field can be cleared. 3.10.2.2 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 3.10.2.3 Power Management Event Indicators Figure 3. simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used ...
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Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17. Please refer to 5.5.8, "Mode Control/Status," on page 123 no energy is present on the line, the PHY is powered down, with ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal reset (22ms). If the software driver polls this bit and it ...
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TX command ‘B’). The TX command instructs the LAN9211 on the handling of the associated buffer. Packet boundaries are delineated using control bits within the TX command. The host provides a 16-bit Packet Tag field in the TX ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Last Buffer in Packet Figure 3.13 Simplified Host TX Flow Diagram 3.12.1 TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes ...
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Host Write Figure 3.14, "TX Buffer noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must be taken into account when calculating the actual TX data FIFO usage. Please ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet TX COMMAND ‘A’ BITS 31 Interrupt on Completion. When set, the TXDONE flag will be asserted when the current buffer has been fully loaded into the TX FIFO. This ...
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TX COMMAND ‘B’ BITS 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in length The final buffer of any transmit ...
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BITS 10 No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present during transmission. Note: During 10/100 Mbps full-duplex transmission, the value of this bit is invalid and should be ignored. 9 Late ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” LAN9211 SMSC 55 DATASHEET Revision 1.93 (11-27-07) ...
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Figure 3.15, "TX Example 1" how data is passed to the TX data FIFO. Data Written to the Ethernet Controller 31 TX Com m and 'A' Buffer End Alignment = 1 Data Start Offset = 7 First Segment = 1 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 3.12.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet single buffer as follows: 2-Byte “Data Start Offset” 183-Bytes ...
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TX Example 3 In this example a single, 111-Byte Ethernet packet will be transmitted with a TX checksum. This packet is divided into four buffers. The four buffers are as follows: Buffer 0: 4-Byte “Data Start Offset” 4-Byte Checksum ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Data Written to the Ethernet Controller 31 TX Command 'A' TX Command 'A' Buffer End Alignment = 1 Data Start Offset = 4 TX Command 'B' First Segment = ...
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TX Data FIFO Underrun If the MIL is not operating in store and forward mode, and the host is unable supply data at the Ethernet line rate, the TX data FIFO can underrun underrun occurs, any ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet The host must use caution when reading the RX data and status. The host must never read more data than what is available in the FIFOs. If this is ...
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Last Packet Figure 3.18 Host Receive Routine Using Interrupts Last Packet Figure 3.19 Host Receive Routine with Polling 3.13.1.1 Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX data FIFO Fast ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for the packet being discarded. For less than 4 DWORDs do ...
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RX Packet Format The RX status words can be read from the RX status FIFO port, while the RX data packets can be read from the RX data FIFO. RX data packets are formatted in a specific manner before ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Host Read Figure 3.21 RX Packet Format with RX Checksum 3.13.3 RX Status Format BITS 31 Reserved. This bit is reserved. Reads 0. 30 Filtering Fail. When set, this ...
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BITS 7 Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet specification of 1518 bytes. This is only a frame too long indication and will not cause the frame reception to be truncated. ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Chapter 4 Internal Ethernet PHY 4.1 Top Level Functional Description Functionally, the internal PHY can be divided into the following sections: 100Base-TX transmit and receive 10Base-T transmit and receive ...
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CODE GROUP SYM 11110 0 0 01001 1 1 10100 2 2 10101 3 3 01010 4 4 01011 5 5 01110 6 6 01111 7 7 10010 8 8 10011 9 9 10110 A A 10111 B B 11010 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet CODE GROUP SYM 01000 V INVALID, RX_ER if during RX_DV 01100 V INVALID, RX_ER if during RX_DV 10000 V INVALID, RX_ER if during RX_DV 4.2.2 Scrambling Repeated data patterns ...
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RX_CLK MAC Internal MII 25MHz by 4 bits MLT-3 NRZI NRZI Converter Converter A/D Magnetics MLT-3 Converter 4.3 100Base-TX Receive The receive data path is shown in 4.3.1 100M Receive Input The MLT-3 from the cable is fed into the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception ...
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TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner. 4.4.3 10M Transmit Drivers The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal Serial Management Interface (SMI). The results of the negotiation process ...
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Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN9211 does not support “Next Page" capability. 4.7 Parallel Detection If the LAN9211 is connected to a device lacking the ability to ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet MODE SPEED Manual 10 Mbps Manual 10 Mbps Manual 10 Mbps Manual 10 Mbps Manual 100 Mbps Manual 100 Mbps Manual 100 Mbps Manual 100 Mbps Auto-Negotiation 10 Mbps ...
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The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9211 is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Chapter 5 Register Description The following section describes all LAN9211 registers and data ports. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h 3Ch 24h 20h ...
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Register Nomenclature and Access Attributes SYMBOL RO Read Only register is read only, writes to this register have no effect. WO Write Only register is write only, reads always return 0. R/W Read/Write: A register ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3 System Control and Status Registers Table 5.1, "Direct Address Register bus. BASE ADDRESS + OFFSET SYMBOL 50h ID_REV 54h IRQ_CFG 58h INT_STS 5Ch INT_EN 60h RESERVED 64h BYTE_TEST ...
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ID_REV—Chip ID and Revision Offset: This register contains the ID and Revision fields for this design. BITS 31-16 Chip ID. This read-only field identifies this design 15-0 Chip Revision 5.3.2 IRQ_CFG—Interrupt Configuration Register Offset: This register configures and indicates ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS 4 IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When IRQ ...
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INT_STS—Interrupt Status Register Offset: This register contains the current status of the generated interrupts. Writing the corresponding bits acknowledges and clears the interrupt. BITS 31 Software Interrupt (SW_INT). This interrupt is generated when the SW_INT_EN bit ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS 12 Reserved 11 TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data FIFO underruns Data FIFO Overrun Interrupt (TDFO). Generated when the TX data ...
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INT_EN—Interrupt Enable Register Offset: This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.5 BYTE_TEST—Byte Order Test Register Offset: This register can be used to determine the byte ordering of the current configuration BITS 31:0 Byte Test 5.3.6 FIFO_INT—FIFO Level Interrupts Offset: ...
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RX_CFG—Receive Configuration Register Offset: This register controls the LAN9211 receive engine. BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9211 will add extra DWORDs ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.8 TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9211 Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears ...
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HW_CFG—Hardware Configuration Register Offset: Note: The transmitter and receiver must be stopped before writing to this register. Refer to 3.12.9, "Stopping and Starting the Transmitter," on page 60 Starting the Receiver," on page 66 BITS 31 Reserved 30 Reserved ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS 16-19 TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of ...
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BITS 0 Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset generates a full reset of the MAC CSR’s. The SCSR’s (system command and status registers) are reset except for any NASR bits. Soft reset also clears ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.9.1 Allowable settings for Configurable FIFO Memory Allocation TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user must select the FIFO ...
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In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host. As space in the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9211 Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used ...
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PMT_CTRL— Power Management Control Register Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9211 Note: The LAN9211 must always be read at least once after power-up, ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS 5-4 WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up event detection as follows 00b -- No wake-up event detected 01b -- Energy detected 10b ...
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GPIO_CFG—General Purpose IO Configuration Register Offset: This register configures the GPIO and LED functions. BITS 31 Reserved 30:28 LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output. When cleared low, the pin functions as a ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS 4:3 GPO Data 3-4 (GPODn). The value written is reflected on GPOn. GPO3 – bit 3 GPO4 – bit 4 2:0 GPIO Data 0-2 (GPIODn). When enabled as ...
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GPT_CNT-General Purpose Timer Current Count Register Offset: This register reflects the current value of the GP Timer. BITS 31-16 Reserved 15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field reflects the current value of the GP Timer. 5.3.17 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.18 FREE_RUN—Free-Run 25MHz Counter Offset: This register reflects the value of the free-running 25MHz counter. BITS 31:0 Free Running SCLK Counter (FR_CNT): Note: This field reflects the value of ...
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MAC_CSR_CMD – MAC CSR Synchronizer Command Register Offset: This register is used to control the read and write operations with the MAC CSR’s BITS 31 CSR Busy. When written into this bit, the read or write ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.22 AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: ...
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BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9211 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.3.23 E2P_CMD – EEPROM Command Register Offset: This register is used to control the read and write operations with the Serial EEPROM. BITS 31 EPC Busy: When a 1 ...
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BITS 30-28 EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must not be issued until the previous command completes. This ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS EPC Time-out EEPROM operation is performed, and there is no response from the EEPROM within 30mS, the EEPROM controller will time- out and return to ...
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MAC Control and Status Registers These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port. Table 5.6, "MAC CSR Register accessible through the indexing method using the MAC_CSR_CMD and MAC_CSR_DATA registers (see ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.4.1 MAC_CR—MAC Control Register Offset: Default Value: This register establishes the RX and TX operation modes and controls for address filtering and packet filtering. BITS 31 Receive All Mode ...
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BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9211 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet BITS 7-6 BackOff Limit (BOLMT). The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC has ...
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ADDRH—MAC Address High Register Offset: Default Value: The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.4.3 ADDRL—MAC Address Low Register Offset: Default Value: The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents of this ...
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HASHH—Multicast Hash Table High Register Offset: Default Value: The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.4.6 MII_ACC—MII Access Register Offset: Default Value: This register is used to control the Management cycles to the PHY. BITS 31-16 Reserved 15-11 PHY Address: For every access to ...
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FLOW—Flow Control Register Offset: Default Value: This register controls the generation and reception of the Control (Pause command) frames by the MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification and the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.4.9 VLAN1—VLAN1 Tag Register Offset: Default Value: This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased from 1518 ...
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WUFF—Wake-up Frame Filter Offset: Default Value: This register is used to configure the wake up frame filter. BITS 31-0 Wake-Up Frame Filter (WFF). Wake-Up Frame Filter (WFF). The Wake-up frame filter is configured through this register using an indexing ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.4.13 COE_CR—Checksum Offload Engine Control Register Offset: Default Value: This register controls the transmit and receive checksum offload engines. BITS 31-17 Reserved 16 TX Checksum Offload Engine Enable (TXCOE_EN). ...
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PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown in ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.5.1 Basic Control Register Index (In Decimal): BITS 15 Reset software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits ...
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Basic Status Register Index (In Decimal): BITS 15 100Base-T4 able ability 14 100Base-TX Full Duplex with full duplex full duplex ability. 13 100Base-TX Half Duplex. ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.5.4 PHY Identifier 2 Index (In Decimal): BITS 15-10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI Model Number. Six-bit ...
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Auto-negotiation Link Partner Ability Index (In Decimal): BITS 15 Next Page next page capable next page ability. This device does not support next page ability. 14 Acknowledge link code word received from ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.5.7 Auto-negotiation Expansion Index (In Decimal): BITS 15:5 Reserved 4 Parallel Detection Fault fault detected by parallel detection logic fault detected by parallel detection ...
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Special Modes Index (In Decimal): ADDRESS 15-8 Reserved 7:5 MODE: PHY Mode of operation. Refer to 4:0 PHYAD: PHY Address: The PHY Address is used for the SMI address. MODE MODE DEFINITIONS 000 10Base-T Half Duplex. Auto-negotiation disabled. 001 ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.5.10 Special Control/Status Indications Index (In Decimal): ADDRESS 15 Override AMDIX Strap 0 - AMDIX_EN (pin 52) enables or disables HP Auto MDIX 1 - Override pin 52. PHY ...
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Interrupt Source Flag Index (In Decimal): BITS 15-8 Reserved. Ignore on read. 7 INT7. 1= ENERGYON generated, 0= not source of interrupt 6 INT6. 1= Auto-Negotiation complete, 0= not source of interrupt 5 INT5. 1= Remote Fault Detected, 0= ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 5.5.13 PHY Special Control/Status Index (In Decimal): BITS Reserved 12 Autodone. Auto-negotiation done indication Auto-negotiation is not done or disabled (or not active) 1 ...
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Chapter 6 Timing Diagrams 6.1 Host Interface Timing The LAN9211 supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Reads (nCS or nRD controlled) ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet REGISTER NAME ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT WORD_SWAP FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA LAN9211 SMSC Table ...
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Special Restrictions on Back-to-Back Read Cycles There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9211, ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 6.2 PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the ...
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PIO Burst Reads In this mode, performance is improved by allowing WORD read cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 6.4 RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9211 will read the RX Data FIFO. ...
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RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9211 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Note Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are ...
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TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9211 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 6.8 Reset Timing nRESET Configuration signals Output drive PARAMETER DESCRIPTION T6.1 Reset Pulse Width T6.2 Configuration input setup to nRESET rising T6.3 Configuration input hold after nRESET rising T6.4 ...
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EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9211: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK CSHCKH t ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Output Voltage (VDD_A18, VDD_CORE) Supply Voltage (VDD_A33, VDD_IO) Positive voltage on signal pins, with respect to ground Negative voltage on signal ...
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Power Consumption (Device Only) This section provides typical power consumption values for the LAN9211 in various modes of operation. These measurements were taken under the following conditions: Temperature: ................................................................................................................................... +25°C Device VDD:................................................................................................................................... +3.30V Table 7.1 Power Consumption Device Only ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet 7.4 Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN9211, including the power dissipated by the ...
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DC Electrical Specifications Table 7.3 below lists the worst case current consumption for each of the supplies of the LAN9211. These figures are provided to assist system designers properly design the power supply; they cannot be used to determine ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Table 7.4 I/O Buffer Characteristics (continued) PARAMETER SYMBOL High Output Level V OH OD8 Type Buffer Low Output Level Type Buffer Low Output Level V OL ...
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Clock Circuit The LAN9211 can accept either a 25MHz crystal (preferred MHz single-ended clock oscillator (±50 PPM) input. The LAN9211 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN (pin 55). If the ...
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Datasheet Chapter 8 Package Outline 8.1 56-QFN Package Figure 8.1 56 Pin QFN Package Definition Table 8.1 56 Pin QFN Package Parameters MIN NOMINAL A 0. 0.00 0.02 ...
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Figure 8.2 56 Pin QFN Recommended PCB Land Pattern Revision 1.93 (11-27-07) High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX 146 DATASHEET Datasheet LAN9211 SMSC ...