LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 134

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.93 (11-27-07)
6.5
SYMBOL
t
t
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
ah
In this mode the upper address inputs are not decoded, and any burst read of the LAN9211 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9211. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back read cycles.
RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). When either or both of these control signals go high, they must remain high for the period
specified.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits.
RX Data FIFO Direct PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
DATASHEET
134
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC
Datasheet
UNITS
LAN9211
ns
ns
ns
ns
ns
ns
ns