LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 135

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
LAN9211
asu
dsu
csh
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
PIO writes are used for all LAN9211 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
135
MIN
45
32
13
0
0
7
0
TYP
Revision 1.93 (11-27-07)
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns