LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 32

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.93 (11-27-07)
3.6.2
FIELD
31:28
27:16
15:12
11:0
Transmit Checksum Offload Engine (TXCOE)
The transmit checksum offload engine provides assistance to the CPU by calculating a 16-bit
checksum, typically for TCP, for a transmit Ethernet frame. The TXCOE calculates the checksum and
inserts the results back into the data stream as it is transferred to the MAC.
To activate the TXCOE and perform a checksum calculation, the host must first set the TX checksum
offload engine enable bit (TXCOE_EN) in the
The host then pre-pends a 3 DWORD buffer to the data that will be transmitted. The pre-pended buffer
includes a TX Command ‘A’, TX Command ‘B’, and a 32-bit TX checksum preamble. When bit 14 (CK)
of the TX Command ‘B’ is set in conjunction with bit 13 (FS) of TX Command ‘A’ and bit 16
(TXCOE_EN) of the COE_CR register, the TXCOE will perform a checksum calculation on the
associated packet. When these three bits are set, a 32-bit TX checksum preamble must be pre-pended
to the beginning of the TX packet (refer to
on the handling of the associated packet. Bits 11:0 of the TX checksum preamble define the byte offset
at which the data checksum calculation will begin (TXCSSP). The checksum calculation will begin at
this offset and will continue until the end of the packet. The data checksum calculation must not begin
in the MAC header (first 14 bytes) or in the last 4 bytes of the TX packet. When the calculation is
complete, the checksum will be inserted into the packet at the byte offset defined by bits 27:16 of the
TX checksum preamble (TXCSLOC). The TX checksum cannot be inserted in the MAC header (first
14 bytes) or in the last 4 bytes of the TX packet. If the CK bit is not set in the first TX Command ‘B’
of a packet, the packet is passed directly through the TXCOE without modification, regardless if the
TXCOE_EN is set. An example of a TX packet with a pre-pended TX checksum preamble can be
found in
ethernet controller in four fragments, the first containing the TX Checksum Preamble.
shows how these fragments are loaded into the TX Data FIFO. For more information on the TX
Command ‘A’ and TX Command ‘B’, refer to
If the TX packet already includes a partial checksum calculation (perhaps inserted by an upper layer
protocol), this checksum can be included in the hardware checksum calculation by setting the TXCSSP
field in the TX checksum preamble to include the partial checksum. The partial checksum can be
replaced by the completed checksum calculation by setting the TXCSLOC pointer to point to the
location of the partial checksum.
Note: When the TXCOE is enabled, the third DWORD of the pre-pended packet is not transmitted.
Note: When the TXCOE is enabled, the store and forward mode must be enabled (bit 20 (SF) of the
RESERVED
TXCSLOC - TX Checksum Location
This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The
checksum will replace two bytes of data starting at this offset.
Note:
RESERVED
TXCSSP - TX Checksum Start Pointer
This field indicates start offset, in bytes, where the checksum calculation will begin in the associated
TX packet.
Note:
However, 4 bytes must be added to the packet length field in TX Command ‘B’.
HW_CFG—Hardware Configuration Register
Section 3.12.6.3, "TX Example
The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4
bytes of the TX packet.
The data checksum calculation must not begin in the MAC header (first 14 bytes) or in
the last 4 bytes of the TX packet.
Table 3.7 TX Checksum Preamble
DATASHEET
Table
3". In this example the host writes the packet data to the
32
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
DESCRIPTION
Section 3.12.2, "TX Command
COE_CR—Checksum Offload Engine Control
3.7). The TX checksum preamble instructs the TXCOE
must be set).
Format".
SMSC
Figure 3.17
Datasheet
LAN9211
Register.