LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 14

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LAN9211_0711

Manufacturer Part Number
LAN9211_0711
Description
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Manufacturer
SMSC [SMSC Corporation]
Datasheet
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
1.10
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9211 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9211 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits
wide. The LAN9211 can be interfaced to either Big-Endian or Little-Endian processors and includes
mixed endian support for FIFO accesses.
LAN9211
Revision 1.93 (11-27-07)
14
SMSC
DATASHEET

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