LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 89

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
16-19
15-14
13-12
BITS
11-2
1
LAN9211
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See
Configurable FIFO Memory Allocation," on page 91
Reserved
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
Reserved
Soft Reset Timeout (SRST_TO).
is not in the operational state (RX_CLK and TX_CLK running), the reset will not
complete and the soft reset operation will timeout and this bit will be set to a ‘1’. The
host processor must correct the problem and issue another soft reset.
[13]
[13]
0
0
1
1
0
0
1
1
[12]
[12]
0
1
0
1
0
1
0
1
DESCRIPTION
If a software reset is attempted when the PHY
Section 5.3.9.1, "Allowable settings for
DATASHEET
Threshold (DWORDS)
Threshold (DWORDS)
89
020h
040h
080h
100h
012h
018h
020h
028h
for more information.
TYPE
R/W
R/W
RO
RO
RO
Revision 1.93 (11-27-07)
DEFAULT
5h
00
0
-
-