LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 117

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
5.4.13
31-17
BITS
15-2
16
1
0
LAN9211
Reserved
TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE.
This bit may only be changed if the TX data path is disabled.
0: The TXCOE is bypassed
1: The TXCOE is enabled
Note:
Reserved
RX Checksum Offload Engine Mode (RXCOE_MODE) This register indicates whether the RXCOE
will check for VLAN tags or a SNAP header prior to beginning its checksum calculation. In its default
mode, the calculation will always begin 14 bytes into the frame.
The RXCOE_MODE may only be changed if the ESS RX path is disabled.
0: Begin checksum calculation after first 14 bytes of Ethernet Frame
1: Begin checksum calculation at start of L3 packet by adjusting for VLAN tags and/or SNAP header.
RX Checksum Offload Engine Enable (RXCOE_EN). This bit enables/disables the Receive COE.
This bit may only be changed if the RX data path is disabled.
0: The RXCOE is bypassed
1: The RXCOE is enabled
Note:
COE_CR—Checksum Offload Engine Control Register
This register controls the transmit and receive checksum offload engines.
Offset:
Default Value:
When the TXCOE is enabled, the store and forward mode must be enabled (bit 20 (SF) of
the
When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of
the
simultaneously.
HW_CFG—Hardware Configuration Register
MAC_CR—MAC Control
D
00000000h
DATASHEET
Register) and vice versa. These functions cannot be enabled
117
DESCRIPTION
Attribute:
Size:
must be set).
R/W
32 bits
Revision 1.93 (11-27-07)