LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 88

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.93 (11-27-07)
5.3.9
27-25
23-22
BITS
31
30
29
28
24
21
20
Reserved
Reserved
FIFO Port Endian Ordering (FPORTEND). This control bit determines the
endianess of RX and TX data FIFO host accesses when accessed through
the RX/TX Data FIFO ports, including the alias addresses (any access from
00h to 3Ch). When this bit is cleared, data FIFO port accesses utilize little
endian byte ordering. When this bit is set, data FIFO port accesses utilize
big endian byte ordering. Please refer to section
Endian Support," on page 33
Direct FIFO Access Endian Ordering (FSELEND). This control bit
determines the endianess of RX and TX data FIFO host accesses when
accessed using the FIFO_SEL signal. When this bit is cleared, FIFO_SEL
accesses utilize little endian byte ordering. When this bit is set, FIFO_SEL
accesses utilize big endian byte ordering. Please refer to section
3.7.3, "Mixed Endian Support," on page 33
feature.
Reserved
AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
Reserved
Transmit Threshold Mode (TTM). This bit is used to control the transmit
threshold the MIL uses as shown in the two tables in the TR field of this
register. This bit is ignored when the SF bit is set (1).
This bit should be set to '1' when operating in 10Mbps mode, and cleared
to '0' when operating in 100Mbps mode if the SF bit cleared.
Store and Forward (SF). When set, this bit instructs the MIL to store a
frame of transmit data in the MIL buffer before forwarding to its final
destination.
If this bit is set, the MIL buffers the entire frame before transmitting. TTM
and TR (see bits 21,13, and 12) are treated as Don’t Cares once the SF
mode is selected.
If this bit is reset, the MAC initiates transmission before it receives the entire
frame from the HBI (Host Bus Interface). TTM and TR (see bit 21,13, and
12) determine when the MIL initiates the transmission. If the host cannot
keep up with the MAC transmitting the Ethernet Packet, there is a risk of an
Underrun Error.
Note:
HW_CFG—Hardware Configuration Register
Note: The transmitter and receiver must be stopped before writing to this register. Refer to
Offset:
This bit must be set when using the TXCOE. Refer to
3.6.2, "Transmit Checksum Offload Engine (TXCOE)"
information.
3.12.9, "Stopping and Starting the Transmitter," on page 60
Starting the Receiver," on page 66
for more information on this feature.
DESCRIPTION
74h
DATASHEET
for more information on this
88
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
for details on stopping the transmitter and receiver.
Section 3.7.3, "Mixed
Size:
for additional
Section
Section
and
32 bits
Section 3.13.4, "Stopping and
NASR
NASR
TYPE
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
SMSC
DEFAULT
AMDIX
Strap
Pin
Datasheet
LAN9211
0
0
0
0
-
-
-
Section