MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 163

• Manufacturer Part Number: MC68HC908KX2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

11.6 COP Control Register
11.7 Interrupts
11.8 Monitor Mode
11.9 Low-Power Modes
11.9.1 Wait Mode
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Address: $FFFF
The COP control register (COPCTL) is located at address $FFFF and
overlaps the reset vector. Writing any value to $FFFF clears the COP
counter and stages 12–5 of the COP prescaler and starts a new timeout
period. Reading location $FFFF returns the low byte of the reset
vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
pin.
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
Reset:
Read:
Write:
Computer Operating Properly Module (COP)
Bit 7
Figure 11-2. COP Control Register (COPCTL)
6
5
Low byte of reset vector
Unaffected by reset
Clear COP counter
Computer Operating Properly Module (COP)
4
3
TST
is present on the IRQ1
2
COP Control Register
1
Technical Data
Bit 0
163