MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 93

• Manufacturer Part Number: MC68HC908KX2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

6.7.2 Stop Mode
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
NOTE:
In stop mode, the SIM counter is held in reset and the CPU and
peripheral clocks are held inactive. If the STOPOSCEN bit in the
configuration register is not enabled, the SIM also disables the internal
clock generator module outputs (CGMOUT and CGMXCLK).
The CPU and peripheral clocks do not become active until after the stop
delay timeout. Stop mode is exited via an interrupt request from a
module that is still active in stop mode or from a system reset.
An interrupt request from a module that is still active in stop mode can
cause an exit from stop mode. Stop recovery time is selectable using the
SSREC bit in the configuration register. If SSREC is set, stop recovery
is reduced from the normal delay of 4096 CGMXCLK cycles down to 32.
Stacking for interrupts begins after the selected stop recovery time has
elapsed.
When stop mode is exited due to a reset condition, the SIM forces a long
stop recovery time of 4096 CGMXCLK cycles.
Short stop recovery is ideal for applications using canned oscillators that
do not require long startup times for stop mode. External crystal
applications should use the full stop recovery time by clearing the
SSREC bit.
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
CPUSTOP
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
R/
IDB
IAB
System Integration Module (SIM)
STOP ADDR
Figure 6-14. Stop Mode Entry Timing
Figure 6-14
PREVIOUS DATA
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
System Integration Module (SIM)
SAME
SAME
Low-Power Modes
SAME
Technical Data
SAME
93