MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 92
MC68HC908KX2
Manufacturer Part Number
MC68HC908KX2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908KX2.pdf
(311 pages)
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System Integration Module (SIM)
Technical Data
92
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode can also be exited by a reset. If the COP disable bit, COPD,
in the configuration register is logic 0, then the computer operating
properly module (COP) is enabled and remains active in wait mode.
Figure 6-12
EXITSTOPWAIT
Note: EXITSTOPWAIT = CPU interrupt
CGMXCLK
R/
IAB
IDB
Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
IDB
IAB
IRST
IAB
IDB
$A6
System Integration Module (SIM)
WAIT ADDR
$A6
Figure 6-13. Wait Recovery from Internal Reset
and
Figure 6-12. Wait Recovery from Interrupt
$DE0B
$A6
PREVIOUS DATA
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
$DE0B
$A6
Figure 6-11. Wait Mode Entry Timing
Figure 6-13
$A6
WAIT ADDR + 1
$A6
$DE0C
$01
show the timing for WAIT recovery.
NEXT OPCODE
$00FF
64
$0B
SAME
$00FE
$DE
SAME
$00FD
RST VCT H RST VCT L
SAME
$00FC
SAME
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