MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 86

• Manufacturer Part Number: MC68HC908KX2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

System Integration Module (SIM)
6.4.1.5 Forced Monitor Mode Entry Reset (MENRST)
6.4.1.6 Low-Voltage Inhibit (LVI) Reset
6.5 SIM Counter
6.5.1 SIM Counter During Power-On Reset
Technical Data
86
The MENRST module is monitoring the reset vector fetches and will
assert an internal reset if it detects that the reset vectors are erased
($FF). When the MCU comes out of reset, it is forced into monitor mode.
See
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The MCU is
held in reset until V
until the SIM counts 4096 CGMXCLK to begin a reset recovery. Another
64 CGMXCLK cycles later, the CPU is released from reset to allow the
reset vector sequence to occur. See
(LVI).
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the internal clock generator to drive the bus clock
state machine.
Section 18. Monitor ROM
DD
voltage falls to the V
System Integration Module (SIM)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
DD
rises above V
TRIPF
(MON).
voltage. The LVI bit in the SIM reset
TRIPR.
Section 8. Low-Voltage Inhibit
The MCU remains in reset
MOTOROLA