SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 10

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Product Overview
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7.
8.
9.
10. Ethernet Media Access Control (MAC) 10/100: this peripheral is compatible with IEEE
11. ADC: 8 bit resolution, 230 Ksps (Kilo-sample per second), with 16 analog input
12. UART's: 3 independent interfaces, up to 115 Kbps each, support Software Flow
13. I²C supports Master mode protocol in Low and Full speed.
14. 6 General Purpose I/O signals are available for user configuration.
15. Embedded features: Real Time Clock, Watchdog, 4 General Purpose Timers.
16. Customizable Logic: it consists of an embedded macro where it is possible to map up
The PHY is integrated.
The Multi-Port Memory Controller block has a programmable arbitration scheme and
the transactions happen on a different layer from the main bus.
Serial Peripheral Interface: it allows a serial connection to ROM and Flash.
The block is connected as a slave on the main AHB Bus, through the Bus Matrix.
The default bus size is 32 bit wide and the accessible memory is 64 MB at a maximum
speed of 50 MHz
USB 2.0 Hosts: these peripherals are compatible with USB 2.0 High-Speed
specification. They can work simultaneously either in Full-Speed or in High-Speed
mode.
The peripherals have dedicated channels to the Multi-Port Memory Controller and 4
slave ports for CPU programming.
The PHYs are embedded.
USB 2.0 Device: the peripheral is compatible with USB 2.0 High-Speed specifications.
A dedicated channel connects the peripheral with the Multi-Port Memory Controller and
registers.
An USB-Plug Detector block is also available to verify the presence of the VBUS
voltage.
The port is provided with the following endpoints on the top of the endpoint 0:
–
–
802.3 standard and supports the MII management interface for the direct configuration
of the external PHY.
It is connected to the Multi-Port Memory Controller through a dedicated channel.
The Ethernet controller and the configuration registers are accessible from the main
AHB Bus.
channels. Connected to APB bus.
Control.
Connected to APB bus.
Connected to APB bus.
Connected to APB bus.
All blocks are interfaced with APB Bus.
to 200K equivalent ASIC gates. The same logic can be alternatively used to implement
32 KBytes of SRAM. Logic gates and RAM bits can be mixed in the same configuration
so that processing elements, tightly coupled with embedded memories, can be easily
implemented.
The MacroCell has 2 dedicated buses, each of them connected with a 4 channel DMA
in order to speed up the data flow with the main memories.
8 interrupt lines and 112 dedicated general purpose I/Os are available.
To allow a simple development of project, customizable logic can be emulated by an
external FPGA, where customer can map his logic; FPGA is easy linkable and keeps
the access to all on-chip and I/Os interfaces of the macro.
3 bulkin / bulkout endpoints
2 isochronous endpoints
SPEAR-09-H022