SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 56

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

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2
C controller
I
Master Mode
The I²C clock is generated by the master peripheral.
The interface operates in Master mode through the generation of the Start condition: Start
bit set to 1 in the control register and I²C not busy (Busy flag set to 0).
Once the Start condition is sent, if interrupts are enabled, an Event Flag bit and a Start bit
are set by hardware. Then the master waits for a read of the register used to observe bus
activity (SR1 register) followed by a write in the data register DR with the Slave address
byte, holding the SCL line low (see
address byte is sent to the SDA line via the internal shift register.
After completion of these transfers, the Event Flag bit is set by hardware with interrupt
generation. Then the master waits for a read of the SR1 register followed by a write in the
control register CR (for example set the Peripheral Enable bit), holding the SCL line low
(see
Next the Master must enter Receiver or Transmitter mode.
Master Receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the Master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
1) Acknowledge pulse if the acknowledge bit ACK in the control register is set
2) Event Flag and the Byte Transfer Finish bits are set by hardware with an interrupt.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see
To close the communication: before reading the last byte from the DR register, set the Stop
bit to generate the Stop condition.
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master Transmitter
Following the address transmission and after SR1 register has been read, the Master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see
When the acknowledge bit is received, the interface sets Event Flag and the Byte Transfer
Finish bits with an interrupt.
To close the communication: after writing the last byte to the DR register, set the Stop bit to
generate the Stop condition.
2
C functional description
Figure 17
Transfer sequencing EV6).
Figure 17
Figure 17
Figure 17
Transfer sequencing EV7).
Transfer sequencing EV8).
Transfer sequencing EV5). Then the slave
SPEAR-09-H022