SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 47

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPEAR-09-H022
13.2
At power on the boot code is enabled from the static memory Bank0 by default; this has to
be a Flash bank memory. Moreover, at power on, the memory clock signal is 19 MHz, the
Release Deep Power-Down is 29 µs and the base address for external memories is 0.
SMI description
The main components of the SMI are two:
Figure 12. Block diagram
–
–
The SMI CLOCK PRESCALER, which sets-up the memory clock
The SMI DATA PROCESSING & CONTROL, which is the logic controlling the
transfer of the data
SPI memories
47/71