SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 48

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPI memories
13.2.1
13.2.2
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Transfer rules
The following rules apply to the access from the AHB to the SPI Controller:
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If instead of Flash memories are used EEPORMs, the address for a Read has to be
ADDRESS + 1 while we want to read the one located at ADDRESS.
The communication protocol used is SPI in CPOL = 1 and CPHA = 1 mode.
The instructions supported are listed in Table 2. SMI Supported instructions.
Table 14.
Memory map
External memory is mapped in AHB address space as shown in
Figure 13. Memory map
03
0B
05
06
02
AB
Endianness is fixed to Little-Endian
SPLIT / RETRY responses are not supported
Bursts must not cross bank boundaries
Size of data transfers for memories can be byte / half-word / word
Size of data transfers for registers must be 32 bit wide
Read Requests: all types of BURST are supported. Wrapping bursts take more time
than incrementing bursts, as there is a break in the address increment
Write Requests: wrapping bursts are not supported, and provoke an ERROR response
on HRESP
When BUSY transfer: the SPI Controller is held until busy is inactive
OPCODE
SMI Supported instructions
Read data bytes
Read data high speed
Read status register
Write enable
Page program
Release from deep
power-down
DESCRIPTION
Figure
13.
SPEAR-09-H022