SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 55

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPEAR-09-H022
18.2
Operating mode
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated by software.
The first byte following the start condition is the address byte; it is always transmitted in
Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter.
Figure 16. I
Acknowledge may be enabled and disabled by software.
The I
The speed of the I
Fast (100 - 400 KHz).
SDA / SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data Register.
The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on
the I
When the I
drain output or floating input. In this case, the value of the external pull-up resistance used
depends on the application.
2
2
C bus mode.
C interface address and / or general call address can be selected by software.
2
C cell is enabled, the SDA and SCL ports must be configured as floating open-
2
C timing
2
C interface may be selected between Standard (0 - 100 KHz) and
I
2
C controller
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