SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 38
SPEAR-09-H022_06
Manufacturer Part Number
SPEAR-09-H022_06
Description
SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.SPEAR-09-H022_06.pdf
(71 pages)
- Current page: 38 of 71
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Vectored interrupt controller
10.2
10.3
38/71
Vector interrupt controller flow sequence
The following procedure shows the sequence for the vectored interrupt flow:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Return from the interrupt. This re-enables the interrupts
Simple interrupt flow sequence
The following procedure shows the sequence for the simple interrupt flow:
1.
2.
3.
4.
5.
6.
7.
8.
9.
An interrupt occurs
The CPU branches to either the IRQ or FIQ Interrupt Vector
If the Interrupt is an IRQ, CPU read the VICVectAddr register and branch to the
interrupt service routine. This can be done using a LDR PC instruction. Reading the
VICVectAddr register updates the interrupt controllers hardware priority register
Stack the Workspace so that the IRQ interrupts can be re-enabled
Enable the IRQ interrupts so that a higher priority can be serviced
Execute the Interrupt Service Routine (ISR)
Clear the Requesting Interrupt in the peripheral, or write to the VICSoftIntClear register
if the request was generated by a software interrupt
Disable the Interrupts and Restore the Workspace
Write to the VICVectAddr register. This clears the respective interrupt in the internal
interrupt priority
An interrupt occurs
Branch to IRQ or FIQ interrupt vector
Branch to the Interrupt Handler
Interrogate the VICIRQStatus register to determine which source generated the
interrupt, and prioritize the interrupts if there are multiple active interrupt sources. This
takes a number of instructions to compute
Branch to the correct ISR
Execute the ISR
Clear the interrupt. If the request was generated by a software interrupt, the
VICSoftIntClear register must be written too
Check the VICIRQStatus register to ensure that no other interrupt is active. If there is
an active request go to Step 4
Return from Interrupt
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