SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 41

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPEAR-09-H022
11.2
DMA control state machine
Figure 8.
The DMA control SM is always reset into the IDLE state.
As a channel request is asserted, SM moves to READ state and the AHB Master will start a
data packet transfer; SM selects appropriate source address.
When SM is in WRITE state, it selects the destination address and the data width from the
Data Stream register and the AHB Master will transfer all data from the FIFO to the
destination.
When the AHB Master has transferred the data packet, it asserts a Packend signal and the
SM will move to the next state, which depends on the channel request signals.
The state transitions from the READ or WRITE states can occur only when a whole data
packet has been transferred.
Figure 9.
DMA State Machine diagram
Data packet transfer
DMA controller block
41/71