SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 45

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPEAR-09-H022
12.3
SSTLL PAD CONFIGURATION
The Stub Series-Terminated Logic (SSTL) interface standard is intended for high-speed
memory interface applications and specifies switching characteristics such that operating
frequencies up to 200 MHz are attainable.
The primary application for SSTL devices is to interface with SDRAMs.
In SPEAr Head200 SSTL pads are used for pins:
●
●
●
●
To enable the 2.5V SSTL mode the least significant bit has to be set to 0; when this bit is
sets to 1 the 3.3V CMOS mode is enabled.
It is also possible to program the pad output impedance. Each pad has two configurable
inputs to change output impedance: ZOUTPROGB and ZOUTPROGA.
Below the table to configure output impedance:
Table 12.
MPMCDATA[15:0]
MPMCADDROUT
MPMCCLKOUT
nMPMCCLKOUT
ZOUTPROGA
Output impedance configuration
0
0
1
1
ZOUTPROGB
0
1
0
1
Multi-Port Memory Controller
OUTPUT BUFFER
IMPEDANCE
25Ω
35Ω
45Ω
55Ω
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