SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 64

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Customizable logic
24.3
64/71
All the above scenarios can be mixed in the same FPGA configuration
●
Figure 19. Emulation with external FPGA
Customization process
The customization process requires two separate steps, executed at different times:
1.
2.
The step 1 defines the interconnection between the customizable logic cells and is executed
at fabrication level on top of the silicon wafers stored in the fab.
The step 2 defines the logic function for each customizable logic cell and is executed after
that the system has been powered up by dedicated software routines running on the
ARM926 microprocessor.
Both Bitstream and VIA-mask realize the user-defined customization for the entire device.
The eASIC™ mapping flow starts from the RTL description of the user-defined
customization, with the purpose to generate the VIA-mask and configuration Bitstream.
can be tested in order to verify the accordance with eASIC™ MacroCell features, by
running the ARM926EJ-S software debugger on a PC connected to SPEAr Head200.
Once this test has been completed successfully, then the user-defined logic is ready to
be moved without any additional changes within the on-chip eASIC™ configurable
logic.
Programming layer fabrication (single VIA-mask).
Bitstream download.
FPGA
Custom
Design
Configuration pin set to
Development Mode
AHB BUS
AHB BUS
SPEAr™ Head
eASIC™
SPEAR-09-H022