SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 63

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPEAR-09-H022
24
24.1
24.2
24.2.1
24.2.2
Customizable logic
Overview
The Customizable Logic consists of an embedded macro where it is possible embedding a
custom project by mapping up to 200K equivalent ASIC gates (corresponding at 16K LUT).
The logic is interfaced with the rest of the system so that can be implemented:
●
●
●
●
●
●
●
All of the above configuration scenarios can be mixed together in the same user-defined
logic.
Custom project development
There are 2 ways to develop a project to embed in SPEAr Head200: through SPEAr Head
behavioral model or through external FPGA.
SPEAr Head behavioral model
In the first case ST provides behavioral model of the fixed architecture allowing the final user
to verify custom logic. Verification procedure is the same as a standard ASIC flow
External FPGA
The custom project to design in the customizable logic can be implemented on an external
FPGA, which emulates eASIC™ logic cells. The purpose of this characteristic is allowing
the user to develop his project both under real-time constraints and compliant to eASIC™
MacroCell features.
This mode is enabled by using the GPIO interface, which is internally configured to support
full-master and full-slave AHB ports.
described behavior. In order to enable the "development mode", the configuration pin has to
be set to state logic 1. After this configuration the logic implemented in the external FPGA
●
AHB sub-systems with masters and slaves (via 1 AHB full master, 1 AHB full slave, 1
AHB master lite, 2 AHB slave ports)
AHB master lite connected to DRAM controller
AHB memories (via AHB slave ports) implemented by configuring the logic cells as
SRAM elements.
I/O protocol handlers (via the 112 dedicated GPIO connections)
8 interrupt channels
8 DMA requests
4 independent SRAM data channels (via dedicated connection to on-chip 16 KByte
SRAM)
can completely interact with the following scenarios:
–
–
–
–
AHB sub-systems with masters and slaves connected to the main system bus (full
masters and full slaves peripherals)
I/O protocol handlers (via 112 dedicated FPGA I/Os)
4 interrupt channels
4 DMA requests
Figure 19
Emulation with external FPGA highlights the
Customizable logic
63/71