HD6412350 Hitachi, HD6412350 Datasheet - Page 10

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10 Bus Release........................................................................................................................ 185
iv
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Overview of Bus Control ................................................................................................... 141
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Basic Bus Interface ............................................................................................................ 147
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
DRAM Interface ................................................................................................................ 160
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation..................................................................................................... 168
6.5.11 Refresh Control..................................................................................................... 171
DMAC Single Address Mode and DRAM Interface ......................................................... 174
6.6.1
6.6.2
Burst ROM Interface.......................................................................................................... 176
6.7.1
6.7.2
6.7.3
Idle Cycle ........................................................................................................................... 179
6.8.1
6.8.2
Write Data Buffer Function ............................................................................................... 184
6.10.1 Overview............................................................................................................... 185
Bus Control Register L (BCRL) ........................................................................... 132
Memory Control Register (MCR) ........................................................................ 134
DRAM Control Register (DRAMCR).................................................................. 137
Refresh Timer/Counter (RTCNT) ........................................................................ 140
Refresh Time Constant Register (RTCOR).......................................................... 140
Area Partitioning................................................................................................... 141
Bus Specifications ................................................................................................ 142
Memory Interfaces................................................................................................ 143
Advanced Mode.................................................................................................... 144
Areas in Normal Mode.......................................................................................... 145
Chip Select Signals ............................................................................................... 146
Overview............................................................................................................... 147
Data Size and Data Alignment.............................................................................. 147
Valid Strobes........................................................................................................ 149
Basic Timing......................................................................................................... 150
Wait Control.......................................................................................................... 158
Overview............................................................................................................... 160
Setting DRAM Space............................................................................................ 160
Address Multiplexing............................................................................................ 160
Data Bus................................................................................................................ 161
Pins Used for DRAM Interface ............................................................................ 161
Basic Timing......................................................................................................... 162
Precharge State Control ........................................................................................ 163
Wait Control ......................................................................................................... 164
Byte Access Control ............................................................................................. 166
When DDS = 1...................................................................................................... 174
When DDS = 0...................................................................................................... 175
Overview............................................................................................................... 176
Basic Timing......................................................................................................... 176
Wait Control.......................................................................................................... 178
Operation .............................................................................................................. 179
Pin States in Idle Cycle ......................................................................................... 183