HD6412350 Hitachi, HD6412350 Datasheet - Page 329

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

8.3.12
(1) Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1
[2] Set the start address of the register information at the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
[5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
(2) Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing
= 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can
have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set
the SCI RDR address in SAR, the start address of the RAM area where the data will be
received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from
RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag
is automatically cleared to 0.
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
Examples of Use of the DTC
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