HD6412350 Hitachi, HD6412350 Datasheet - Page 563

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

13.2.7
Note: Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, and in standby mode or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
0
1
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
0
1
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
Bit
Initial value
R/W
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Serial Status Register (SSR)
Description
[Clearing conditions]
[Setting conditions]
Description
[Clearing conditions]
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
:
:
:
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
R/(W)*
TDRE
7
1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
FER
4
0
R/(W)*
PER
3
0
TEND
R
2
1
MPB
R
1
0
(Initial value)
(Initial value)
MPBT
R/W
0
0
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