HD6412350 Hitachi, HD6412350 Datasheet - Page 300

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

Figure 7-40 shows an example in which a low level is not output at the TEND pin.
Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in
synchronization with DMAC internal operations. The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed by detection of a low level.
Activation Source Acceptance: At the start of activation source acceptance, a low level is
detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an
internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an
internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to
enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
280
to [2].
switches to [1].
Internal write signal
Internal read signal
External address
Figure 7-40 Example in Which Low Level is Not Output at TEND Pin
Internal address
HWR, LWR
TEND
ø
External write by CPU, etc.
Not output
DMA
read
DMA
write