HD6412350 Hitachi, HD6412350 Datasheet - Page 413

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port G Register (PORTG)
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PG
0
Modes 3 and 7 [H8S/2351 only]
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4 and 5 [H8S/2350]; modes 4, 5, and 6 [H8S/2351]
Pins PG
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Pin PG
setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit
to 0 makes the pin an input port. For details of the DRAM interfaces, see section 6, Bus
Controller.
).
0
4
functions as the CAS output pin when DRAM interface is designated. Otherwise,
to PG
:
:
:
:
:
:
Undefined
Undefined
1
function as bus control output pins (CS0 to CS3) when the corresponding
—
—
—
—
7
7
Undefined
Undefined
—
—
—
—
6
6
4
to PG
Undefined
Undefined
4
—
—
—
—
5
5
to PG
0
) must always be performed on PGDR.
0
PG4DR
.
R/W
PG4
—*
R
4
0
4
PG3DR
PG3
R/W
—*
R
3
0
3
PG2DR
PG2
R/W
—*
R
2
0
2
PG1DR
PG1
R/W
—*
R
1
0
1
PG0DR
4
PG0
R/W
—*
to
R
0
0
0
393