HD6412350 Hitachi, HD6412350 Datasheet - Page 310

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

8.2.6
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
1
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number
generated for each interrupt controller.
290
Bit
Initial value
R/W
Bit
Initial value
R/W
DTC Transfer Count Register B (CRB)
DTC Enable Registers (DTCER)
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
:
:
:
:
:
:
Unde-
When the DISEL bit is 1 and the data transfer has ended
When the specified number of transfers have ended
fined
15
—
DTCE7
R/W
Unde-
7
0
fined
14
—
Unde-
fined
13
—
DTCE6
R/W
Unde-
6
0
fined
12
—
Unde-
fined
11
—
DTCE5
R/W
Unde-
5
0
fined
10
—
Unde-
fined
—
9
DTCE4
R/W
Unde-
4
0
fined
—
8
Unde-
fined
—
7
DTCE3
R/W
3
0
Unde-
fined
—
6
Unde-
fined
—
DTCE2
5
R/W
2
0
Unde-
fined
—
4
Unde-
fined
—
3
DTCE1
R/W
Unde-
1
0
fined
—
2
Unde-
(Initial value)
fined
—
DTCE0
1
(n = 7 to 0)
R/W
0
0
Unde-
fined
—
0