HD6432646 Hitachi, HD6432646 Datasheet - Page 10

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Section
9.13.2 Register
Configuration
15.2.3 Bit
Configuration
Register (BCR)
15.2.11 Interrupt
Register (IRR)
15.2.16 Unread
Message Status
Register (UMSR)
Page
283
539
547
555
Description
Part F Data Register (PFDR)
2nd line changed as follows
PFDR is an 8-bit readable/writable register that stores output data for the port F
pins (PF6 to PF2, PF0).
6th line changed as follows
Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.
Figure of Detailed Description of Timing within 1 Bit, HCAN bit rate calculation,
BCR Setting Constraints, Table of Setting Range for TSEG1 and TSEG2 in
BCR
Moved to Bit Rate and Bit Timing Settings in section 15.3.2, Initialization after
Hardware Reset.
Bit 15—Overload Frame Interrupt Flag: Status flag indicating that the HCAN
has transmitted an overload frame.
Bit 15: IRR7
0
1
Bit table amended and Note added
Initial value:
Initial value:
UMSR
Note: *
Bit
Initial value :
R/W
R/W:
R/W:
Bit:
Bit:
Only 1 can be written, to clear the flag.
:
:
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10
UMSR7
R/(W)*
R/(W)*
R/W
15
—
0
7
0
7
0
Description
[Clearing condition]
Writing 1
Overload frame transmission
[Setting conditions]
When overload frame is transmitted
PF6DR
UMSR6
R/(W)*
R/(W)*
R/W
14
6
0
0
6
0
PF5DR
UMSR5
R/(W)*
R/(W)*
R/W
5
0
13
0
5
0
PF4DR
UMSR4
R/(W)*
R/(W)*
R/W
4
0
12
0
4
0
PF3DR
R/W
UMSR3
R/(W)*
R/(W)*
3
0
11
0
3
0
PF2DR
R/W
UMSR2
R/(W)*
R/(W)*
2
0
10
0
2
0
undefined
—
—
1
UMSR1
R/(W)*
UMSR9
R/(W)*
9
0
1
0
(Initial value)
PF0DR
R/W
0
0
UMSR0
R/(W)*
UMSR8
R/(W)*
8
0
0
0