HD6432646 Hitachi, HD6432646 Datasheet - Page 22

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.3
Section 7
7.1
7.2
7.3
7.4
7.5
7.6
iv
6.2.3
6.2.4
6.2.5
Operation ........................................................................................................................... 135
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Overview............................................................................................................................ 141
7.1.1
7.1.2
7.1.3
7.1.4
Register Descriptions......................................................................................................... 144
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
Overview of Bus Control................................................................................................... 154
7.3.1
7.3.2
7.3.3
7.3.4
Basic Bus Interface............................................................................................................ 158
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Burst ROM Interface ......................................................................................................... 171
7.5.1
7.5.2
7.5.3
Idle Cycle........................................................................................................................... 174
7.6.1
7.6.2
Break Control Register A (BCRA) ...................................................................... 132
Break Control Register B (BCRB) ....................................................................... 134
Module Stop Control Register C (MSTPCRC).................................................... 134
PC Break Interrupt Due to Instruction Fetch........................................................ 135
PC Break Interrupt Due to Data Access ............................................................... 135
Notes on PC Break Interrupt Handling ................................................................ 136
Operation in Transitions to Power-Down Modes ................................................ 136
PC Break Operation in Continuous Data Transfer ............................................... 137
When Instruction Execution is Delayed by One State ......................................... 138
Additional Notes .................................................................................................. 139
Bus Controller..................................................................................141
Features ................................................................................................................ 141
Block Diagram...................................................................................................... 142
Pin Configuration ................................................................................................. 143
Register Configuration ......................................................................................... 143
Bus Width Control Register (ABWCR) ............................................................... 144
Access State Control Register (ASTCR).............................................................. 144
Wait Control Registers H and L (WCRH, WCRL).............................................. 146
Bus Control Register H (BCRH).......................................................................... 150
Bus Control Register L (BCRL)........................................................................... 151
Pin Function Control Register (PFCR) ................................................................ 152
Area Partitioning .................................................................................................. 154
Bus Specifications ................................................................................................ 155
Memory Interfaces................................................................................................ 156
Interface Specifications for Each Area................................................................. 157
Overview .............................................................................................................. 158
Data Size and Data Alignment ............................................................................. 158
Valid Strobes ........................................................................................................ 160
Basic Timing ........................................................................................................ 161
Wait Control ......................................................................................................... 169
Overview .............................................................................................................. 171
Basic Timing ........................................................................................................ 171
Wait Control ......................................................................................................... 173
Operation .............................................................................................................. 174
Pin States During Idle Cycles............................................................................... 177