HD6432646 Hitachi, HD6432646 Datasheet - Page 706

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3: RAMS
0
1
Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together
with bit 3 to select the flash memory area to be overlapped with RAM. (See table 20-4.)
Table 20-4 Flash Memory Area Divisions
Addresses
H'FFE000–H'FFE3FF
H'000000–H'0003FF
H'000400–H'0007FF
H'000800–H'000BFF
H'000C00–H'000FFF
20.5.6
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode.
Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory
power-down mode when the LSI switches to subactive mode. For details, see section 20.12, Flash
Memory and Power-Down States.
672
Initial value:
Flash Memory Power Control Register (FLPWCR)
R/W:
Bit:
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
PDWND
R/W
7
0
Block Name
RAM area 1 kB
EB0 (1 kB)
EB1 (1 kB)
EB2 (1 kB)
EB3 (1 kB)
—
6
0
R
—
5
0
R
RAMS
0
1
1
1
1
—
4
0
R
—
RAM2
*
0
0
1
1
3
0
R
—
2
0
R
RAM1
*
0
1
0
1
—
1
0
R
*: Don't care
(Initial value)
RAM0
*
*
*
*
*
—
0
0
R