HD6432646 Hitachi, HD6432646 Datasheet - Page 600

• Manufacturer Part Number: HD6432646
• Description: (HD64F264x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Example: With a 1 Mb/s baud rate and a 20 MHz input clock:
HCAN bit rate calculation:
BCR Setting Constraints
These constraints allow the setting range shown in table 15-4 for TSEG1 and TSEG2 in BCR.
566
1-bit time
Legend
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal
PRSEG:
PHSEG1:
PHSEG2:
Note: * The time quanta values of TSEG1 and TSEG2 become the value of TSEG + 1.
Note: f
TSEG1 > TSEG2
Bit rate =
1 Mb/s =
Set Values
f
BRP = 0 (B'000000)
TSEG1 = 4 (B'0100)
TSEG2 = 3 (B'011)
SYNC_SEG
CLK
= 20 MHz
1
The BCR values are used for BRP, TSEG1, and TSEG2.
bit edge transitions occur in this segment.)
Segment for compensating for physical delay between networks.
Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronization (resynchronization) is established.)
Buffer segment for correcting phase drift (negative). (This segment is
shortened when synchronization (resynchronization) is established.)
CLK
Figure 15-6 Detailed Description of Timing within 1 Bit
2
2
= ø (system clock)
(0 + 1)
(BRP + 1)
20 MHz
SJW
1-bit time (8–25 time quanta)
(3 + 4 + 3)
PRSEG
TSEG1 (time segment 1)*
(3 + TSEG1 + TSEG2)
(SJW = 0 to 3)
f
CLK
Actual Values
—
System clock
5TQ
4TQ
2–16
PHSEG1
2
TSEG2 (time segment 2)*
PHSEG2
2–8
Quantum