MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 19

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, T
and T
Freescale Semiconductor
Reference clock freq range
Pre-divider output clock
freq range
Double clock freq range
Pre-divider factor (PD)
Total multiplication factor
(MF)
MF
integer part
MF
numerator
MF
denominator
Pre-multiplier lock-in time
Freq lock-in time after
full reset
Freq lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Freq jitter (p-p)
Phase jitter (p-p)
Power supply voltage
Power dissipation
dck
Parameter
is the output double clock period.
Vcc = 1.8V
Vcc = 1.8V
Vcc = 1.8V
–
Includes both integer
and fractional parts
–
Should be less than the
denominator
–
–
FOL mode for non-integer MF
(does not include pre-must lock-in time)
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
FPL mode and integer MF (does not include
pre-multi lock-in time)
FPL mode and integer MF (does not include
pre-multi lock-in time)
–
Integer MF, FPL mode, Vcc=1.8V
–
FOL mode, integer MF,
f
dck
= 200 MHz, Vcc = 1.8V
MC9328MX1 Advance Information, Rev. 4
Table 11. DPLL Specifications
Test Conditions
ref
is a reference clock period after the pre-divider
Minimum
250
220
300
270
1.7
80
5
5
1
5
5
0
1
–
–
–
–
(~50 µs)
Typical
(0.01%)
(56 µs)
(70 µs)
(64 µs)
(10%)
0.005
280
250
350
320
1.0
–
–
–
–
–
–
–
–
–
–
–
Maximum
312.5
1022
1023
0.01
100
220
300
270
400
370
1.5
2.5
30
16
15
15
4
Specifications
2•T
µ
MHz
MHz
MHz
Unit
mW
T
T
T
T
ns
sec
V
–
–
–
–
–
ref
ref
ref
ref
dck
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