MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 8

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Signals and Connections
8
TCK
TMS
BIG_ENDIAN
ETMTRACESYNC
ETMTRACECLK
ETMPIPESTAT [2:0]
ETMTRACEPKT [7:0]
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
CONTRAST
SPL_SPR
Signal Name
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is a static
pin to inner module. If the pin is driven logic-high the memory system is configured into big endian. If
it is driven logic-low the memory system is configured into little endian. The pin is not supposed to
be changed on the fly.
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETM packet signals which are multiplex with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
Frame Sync or Vsync—This signal also serves as the clock signal output for gate.
driver (dedicated signal SPS for Sharp panel HR-TFT).
Line Pulse or H Sync
Shift Clock
Alternate Crystal Direction/Output Enable
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Table 3. Signal Names and Descriptions (Continued)
MC9328MX1 Advance Information, Rev. 4
CMOS Sensor Interface
LCD Controller
System
ETM
Function/Notes
Freescale Semiconductor