MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 65

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

3.15.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response
to the host command starts after exactly N
processed in the open-drain mode. The minimum delay between the host command and card response is NCR
clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52 are defined in Table 30.
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 49 on
page 66, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of
two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card.
The other two diagrams show the separating periods N
Freescale Semiconductor
Symbol
CRC
D
Z
*
Table 30. State Signal Parameters for Figure 48 through Figure 52
High impedance state
Data bits
Repetition
Cyclic redundancy check bits (7 bits)
CMD
CMD
Card Active
Figure 48. Timing Diagrams at Identification Mode
S T
S T
Host Command
Host Command
Definition
Content
Content
MC9328MX1 Advance Information, Rev. 4
ID
clock cycles. For the card address assignment, SET_RCA is also
CRC
CRC
E Z
E Z
RC
N
N
******
******
CR
and N
ID
Symbol
cycles
cycles
S
T
P
E
CC
.
Z S T
Z S T
Start bit (0)
Transmitter bit
(Host = 1, Card = 0)
One-cycle pull-up (1)
End bit (1)
Identification Timing
SET_RCA Timing
CID/OCR
CID/OCR
Content
Content
Host Active
Definition
Z Z
Z Z
Z
Z
Specifications
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